Vlsi design and embedded systems

Download .pdf, .docx, .epub, .txt
Did you like this example?

CHAPTER 1

INTRODUCTION

1.1 Motivation

Phase locked loop (PLL) [1-3] is the heart of the many modern electronics as well as communication system. Recently plenty of the researches have conducted on the design of phase locked loop (PLL) circuit and still research is going on this topic. Most of the researches have conducted to realize a higher lock range PLL with lesser lock time [4] and have tolerable phase noise.

Don’t waste time! Our writers will create an original "Vlsi design and embedded systems" essay for you whith a 15% discount.

Create order

The most versatile application of the phase locked loops (PLL) is for clock generation and clock recovery in microprocessor, networking, communication systems, and frequency synthesizers. Phase locked-loops (PLLs) are commonly used to generate well-timed on-chip clocks in high-performance digital systems. Modern wireless communication systems employ Phase Locked Loop (PLL) mainly for synchronization, clock synthesis, skew and jitter reduction [5]. Phase locked loops find wide application in several modern applications mostly in advance communication and instrumentation systems. PLL being a mixed signal circuit involves design challenge at high frequency.

Since its inspection in early 1930s, where it was used in the synchronization of the horizontal and vertical scans of television, it has come to an advanced form of integrated circuit (IC). Today found uses in many other applications. The first PLL ICs were available around 1965; it was built using purely analog component. Recent advances in integrated circuit design techniques have led to the development of high performance PLL which has become more economical and reliable. Now a whole PLL circuit can be integrated as a part of a larger circuit on a single chip.

There are mainly five blocks in a PLL. These are phase frequency detector (PFD), charge pump (CP), low pass loop filter (LPF), voltage controlled oscillator (VCO) and frequency divider. Presently almost all communication and electronics devices operate at a higher frequency, so for that purpose we need a faster locking PLL. So there are a lot of challenges in designing the mentioned different blocks of the PLL to operate at a higher frequency. And these challenges motivated me towards this research topic. In this work mainly the faster locking of the PLL is concentrated by properly choosing the circuit architectures and parameters. The optimization of the VCO circuit is also carried out in this work to get a better frequency precision.

1.2 Organization of Thesis

Before going into the details of the PLL, the motivation behind this work is mentioned in the Chapter 1 of the thesis. Chapter 2 briefly describes the whole PLL system. An introduction to the PLL circuit is mentioned in the section 2.1. Section 2.2 contains the detail architecture of the whole PLL system. Different types of PLLs are mentioned in the section 2.3. Section 2.4 explains the basic terms used in the PLL system while the consecutive sections give the details about the noise and application of the PLL.

Do you want to see the Full Version?

View full version

Having doubts about how to write your paper correctly?

Our editors will help you fix any mistakes and get an A+!

Get started
Leave your email and we will send a sample to you.
Thank you!

We will send an essay sample to you in 2 Hours. If you need help faster you can always use our custom writing service.

Get help with my paper
Sorry, but copying text is forbidden on this website. You can leave an email and we will send it to you.